Typically, a system-on-chip (SoC) performs several functions simultaneously, for example a video processing function, an audio processing function, a web-browsing function, and a user interface function. Processes associated with each of such functions have different real-time constraints. For example, it is critical for a video frame or an audio sample to be processed on or before a certain deadline, else it may result in image artifacts, jitter, frozen video and generally poor user experience. In another example, web-browsing has higher flexibility as an occasional delay in processing a web request, even if slightly beyond a nominal deadline, is acceptable.
Examples of SoCs are found in various consumer electronic appliances including, but not limited to, mobile phones, smart phones, digital high-definition televisions, set-top boxes, personal digital assistants, and tablet computers. Among other factors, for example processor speed, a speed at which the SoC performs is determined to a large extent based on latency of memory access. The latency of memory access can be defined as length of time between arrival of an access request made to memory and return of associated response from the memory. Overall performance of the SoC is hence dependent on the latency of memory access, with lower latency of memory access resulting in higher SoC performance.
There are multiple clients that access the memory in order to execute different processes associated with the functions of the SoC. Each client makes multiple requests to the memory. Time needed for a client to execute a process depends on the latency for accessing the memory. Some clients have a deadline for executing a process that must be met in order to satisfy real-time constraints. In order to achieve the deadline, average latency for accessing the memory needs to be bounded for a set of consecutive memory accesses. However, other clients do not have such deadlines. In order to serve each client that needs to access the memory, a suitable memory needs to be designed. However, designing such memory is difficult as one or more of the clients have higher deadline sensitivity than others.
Hence, there is a need for providing memory access to multiple clients of differing real-time constraints such that each deadline is met.